1. Field of the Invention
This invention relates to a structure of an integrated circuit (IC), and more particularly to a structure of a dynamic random access memory (DRAM).
2. Description of Related Art
When the function of a micro processor is continuously enhanced and, in accordance with, the abilities of software including the program size and the computing power are increased, the capacitance of memory is enlarged accordingly. As the integration of DRAM is increased, the memory cell for the present development includes a field effect transistor (FET) and a storage capacitor. FIG. 1 is the configuration of the circuit of the memory cell in a DRAM device. In FIG. 1, the selected capacitor C, one of an array of capacitors built on the wafer, can be used to store the data by either charging or discharging the capacitor C. The most common strategy is that a binary data stored on a bit has a logic state of "0" as the capacitor C being discharged and has a logic state of "1" as the capacitor C being charged. In general, a dielectric thin film 101 is sandwiched between an upper electrode 100 and a lower electrode 102 of the capacitor C to provide a required dielectric constant. The capacitor C is coupled to a bit line BL and fulfills the action of read/write through charging or discharging the capacitor C by utilizing the FET T as a switch. The action as described above is done by the following procedure that the FET T is coupled between the bit line BL and the capacitor C which is coupled to the voltage source V. A word line WL is coupled to the gate of FET T to selectively control the connecting status between the bit line BL and capacitor C.
FIG. 2 schematically illustrates a sectional view of a conventional DRAM. Referring to FIG. 2, a DRAM is formed over a substrate 200. The substrate 200 has a starting surface is called a substrate surface, on which a structure of the DRAM is based. Then, an isolation area 202, usually being called as a field oxide (FOX), is formed on the substrate. Next, a gate 204 is formed on the substrate surface. Next, an interchangeable source/drain region is formed below the substrate surface. The interchangeable source/drain region includes a number of separated regions such as the interchangeable source/drain region 206, 207. Next, a dielectric layer 208 is formed over the substrate 200. Next, a contact window 210 is defined on the dielectric layer 208. Next, a conductive layer 212 is formed over the dielectric layer 208 covering and filling the contact window 210 so that it is electrically coupled to the interchangeable source/drain region 206 and is treated as a lower electrode of a capacitor of a DRAM. Next, a dielectric thin film 214 made of one such as silicon-nitride/oxide (NO) or oxide/silicon-nitride/oxide (ONO) is formed over the conductive layer 212. Next, a conductive layer 216 is formed over the dielectric thin film 214 to be treated as an upper electrode and to form a capacitor. Next, a dielectric layer 218 is formed over the substrate 200 and the conductive layer 216. Next, a contact window 220 is defined on the dielectric layer 218 and is filled in a metal layer to act as the BL 222. And next, the conductive layer 216, the upper electrode, is to be coupled to the voltage source V as shown in FIG. 1.
The conventional DRAM as described above needs the conductive layer 216 for the upper electrode, in which the upper electrode needs a connection to the voltage source usually through a metal line. This not only increases the complexity and cost of the fabrication but also increases the layout area of the IC chip. Further, this conventional connection between the upper electrode and the voltage source is no longer efficient for a highly integrated semiconductor product and even causes the degradation of the operation speed due to the distance of the connection being too long.